Arrangement for energy conditioning

ABSTRACT

Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition electrically complementary energy confluences.

TECHNICAL FIELD

[0001] This application is a continuation-in-part of co-pendingapplication Ser. No. 10/023,467, filed Dec. 17, 2001, which is acontinuation-in-part of co-pending application Ser. No. 09/996,355,filed Nov. 29, 2001, which is a continuation-in-part of co-pendingapplication Ser. No. 10/003,711, filed Nov. 17, 2001, which is acontinuation-in-part of co-pending application Ser. No. 09/982,553,filed Oct. 17, 2001.

[0002] In addition, this application claims the benefit of U.S.Provisional Application No. 60/302,429, filed Jul. 2, 2001, U.S.Provisional Application No. 60/310,962, filed Aug. 8, 2001, U.S.Provisional Application No. 60/349,954, filed Jan. 8, 2002, and U.S.Provisional Application No. (Not assigned), filed Jun. 12, 2002.

[0003] This application relates to balanced shielding arrangements thatuse complementary relative groupings of energy pathways, such aspathways for various energy propagations for multiple energyconditioning functions. These shielding arrangements may be operable asdiscrete or non-discrete embodiments that can sustain and conditionelectrically complementary energy confluences.

BACKGROUND

[0004] Today, as the density of electronics within applicationsincreases, unwanted noise byproducts of the increased density may limitthe performance electronic circuitry. Consequently, the avoidance of theeffects of unwanted noise byproducts, such as by isolation orimmunization of circuits against the effects of the undesirable noise isan important consideration for circuit arrangements and circuit design.

[0005] Differential and common mode noise energy may be generated by,and may propagate along or around, energy pathways, cables, circuitboard tracks or traces, high-speed transmission lines, and/or bus linepathways. These energy conductors may act as, for example, an antennathat radiates energy fields. This antenna-analogous performance mayexacerbate the noise problem in that, at higher frequencies, propagatingenergy utilizing prior art passive devices may experience increasedlevels of energy parasitic interference, such as various capacitiveand/or inductive parasitics.

[0006] These increases may be due, in part, to the combination ofconstraints resulting from functionally or structurally limitations ofprior art solutions, coupled with the inherent manufacturing or designimbalances and performance deficiencies of the prior art. Thesedeficiencies inherently create, or induce, unwanted and unbalancedinterference energy that may couple into associated electricalcircuitry, thereby making at least partial shielding from theseparasitics and electromagnetic interference desirable. Consequently, forbroad frequency operating environments, solving these problemsnecessitates at least a combination of simultaneous filtration, carefulsystems layout having various grounding or anti-noise arrangements, aswell as extensive isolating in combination with at least partialelectrostatic and electromagnetic shielding.

[0007] Thus, a need exists for a self-contained, energy-conditioningarrangement utilizing simplified energy pathway arrangements, which mayadditionally include other elements, amalgamated into a discreet ornon-discreet component, which may be utilized in almost any circuitapplication for providing effective, symmetrically balanced, andsustainable, simultaneous energy conditioning functions selected from atleast a decoupling function, transient suppression function, noisecancellation function, energy blocking function, and energy suppressionfunctions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Understanding of the present invention will be facilitated byconsideration of the following detailed description of the preferredembodiments of the present invention taken in conjunction with theaccompanying drawings, in which like numerals refer to like parts and inwhich:

[0009]FIG. 1 is a relative location compass operable for determiningrelative locations of the various pathway extensions disclosed;

[0010]FIGS. 1A-1C show relative locations of the various pathwayextensions disclosed according to an aspect of the present invention;

[0011]FIG. 2A shows a circuit schematic of the plan view of anembodiment of 2B according to an aspect of the resent invention;

[0012]FIG. 2B is a plan view of an embodiment according to an aspect ofthe present invention;

[0013]FIG. 3A shows a circuit schematic of the plan view of anembodiment of 3B according to an aspect of the present invention;

[0014]FIG. 3B is a plan view of an embodiment according to an aspect ofthe present invention;

[0015]FIG. 3C shows a plan view of a shield according to an aspect ofthe present invention;

[0016]FIG. 4A shows a relative plan view of an embodiment according toan aspect of the present invention;

[0017]FIG. 4B shows a relative plan view of an embodiment according toan aspect of the present invention;

[0018]FIG. 4C shows a relative plan view of an embodiment according toan aspect of the present invention;

[0019]FIG. 4D shows a relative plan view of an embodiment according toan aspect of the present invention;

[0020]FIG. 4E shows a relative plan view of an embodiment according toan aspect of the present invention;

[0021]FIG. 4F shows a relative plan view of an embodiment according toan aspect of the present invention;

[0022]FIG. 4G shows a relative plan view of an embodiment according toan aspect of the present invention;

[0023]FIG. 4H shows a relative plan view of an embodiment according toan aspect of the present invention;

[0024]FIG. 41 shows a relative plan view of an embodiment according toan aspect of the present invention;

[0025]FIG. 5A shows a stacked multiple, circuit network including groupsof pathways according to an aspect of the present invention;

[0026]FIG. 5B shows a stacked shield according to an aspect of thepresent invention;

[0027]FIG. 5C shows a relative plan view of a stacked multiple,non-shared circuit network having VIAs including groups of pathwaysaccording to an aspect of the present invention;

[0028]FIG. 6 shows a relative plan view of circuit arrangement variantaccording to an aspect of the present invention; and,

[0029]FIG. 7 shows a relative plan view of circuit arrangement variantaccording to an aspect of the present invention;

DETAILED DESCRIPTION

[0030] This application is a continuation-in-part of co-pendingapplication Ser. No. 10/023,467, filed Dec. 17, 2001, which is acontinuation-in-part of co-pending application Ser. No. 09/996,355,filed Nov. 29, 2001, which is a continuation-in-part of co-pendingapplication Ser. No. 10/003,711, filed Nov. 17, 2001, which is acontinuation-in-part of co-pending application Ser. No. 09/982,553,filed Oct. 17, 2001, each of which is incorporated by reference herein.

[0031] In addition, this application claims the benefit of U.S.Provisional Application No. 60/302,429, filed Jul. 2, 2001, U.S.Provisional Application No. 60/310,962, filed Aug. 8, 2001, U.S.Provisional Application No. 60/349,954, filed Jan. 8, 2002, and U.S.Provisional Application No. (Not assigned), filed Jun. 12, 2002, each ofwhich is incorporated by reference herein.

[0032] It is to be understood that the figures and descriptions of thepresent invention have been simplified to illustrate elements that arerelevant for a clear understanding of the present invention, whileeliminating, for the purpose of clarity, many other elements found intypical energy conditioning systems and methods. Those of ordinary skillin the art will recognize that other elements and/or steps are desirableand/or required in implementing the present invention. However, becausesuch elements and steps are well known in the art, and because they donot facilitate a better understanding of the present invention, adiscussion of such elements and steps is not provided herein. Thedisclosure herein is directed to all such variations and modificationsto such elements and methods known to those skilled in the art.Additionally, it will be apparent to those skilled in the art that termsused herein that may include a whole, or a portion of a whole, such as“energy”, “system”, circuit, and the like, are contemplated to includeboth the portions of the whole, and the entire of the whole, as used,unless otherwise noted.

[0033] As used herein, an “energy pathway” or “pathway” may be at leastone, or a number, of conductive materials, each one operable forsustained propagation of energy. Pathways may be conductive, therebybetter propagating various electrical energies as compared tonon-conductive or semi-conductive materials directly or indirectlycoupled to, or adjacent to, the pathways. An energy pathway mayfacilitate propagation of a first energy by allowing for various energyconditioning functions, such as conditioning functions arising due toany one or a number of aspects, such as, but not limited to, theshielding, the orientation and/or the positioning of the energy pathwayswithin the energy pathway arrangement, which various arrangements havingan orientation and/or positioning thereby allow for interaction of thefirst energy with propagating energies that are complementary to atleast the first energy. An energy pathway may include an energy pathwayportion, an entire energy pathway, a conductor, an energy conductor, anelectrode, at least one process-created conductor, and/or a shield. Aplurality of energy pathways may include a plurality of each device orelement discussed hereinabove with respect to energy pathway. Further,as used generally herein, a conductor may include, for example, anindividual conductive material portion, a conductive plane, a conductivepathway, a pathway, an electrical wire, a via, an aperture, a conductiveportion such as a resistive lead, a conductive material portion, or anelectrical plate, such as plates separated by at least one medium 801,for example.

[0034] A shield may include a shielding electrode, a shielding pathwayportion, a shielded pathway, a shielded conductor, a shielded energyconductor, a shielded electrode, and/or at least one process-createdshielded pathway portion. A plurality of shields may include a pluralityof the devices discussed hereinabove with respect to a shield.

[0035] As used generally herein, a pathway may be complementarypositioned, or complementary orientated, with respect to a main-body 80,81, having various pathway extensions, designated 79“X”, 812“X”, 811“X”and 99“X”. Main-bodies 80, 81 may be in three-dimensional physicalrelationships individually, in pairs, groups, and/or pluralities as todistance, orientation, position, superposition, non-superposition,alignment, partial alignment, lapping, non-lapping, and partial lapping.Superposed main-body pathway 80, may, for example include a pairing ofphysically opposing and oppositely orientated main-body pathways 80 thatare any one of, or any combination of, electrically null, electricallycomplementary, electrically differential, or electrically opposite.

[0036] A pathway arrangement may include at least a shield at leastpartially shielding at least one energy pathway, or a group of shieldsforming a shield structure that at least partially shielding, via aconductive shielding, at least a conductively isolated pairing of atleast two energy pathways, such as vias, apertures or complementarypaired pathways.

[0037] An exemplary embodiment may allow energy propagation on aconductively isolated pairing, such as complementary paired pathways,causing energy propagation on common shields, or at least one groupingof shields, serving an isolated circuit. This embodiment may allow a lowinductance pathway to form among at least a single pair of isolated andseparate parallel pathways serving at least one separate and distinctisolated circuit system. An exemplary embodiment may allow for thedevelopment of at least a low inductance pathway for utilization ofenergy propagating on at least one parallel pathway of at least two setsof isolated and separate parallel pathways and the development along atleast one parallel pathway of at least one other low inductance pathwayfor utilization of energy propagating along at least one other separateand distinct isolated circuit system.

[0038] An exemplary embodiment utilized as part of a circuit assemblymay have at least one pathway of relatively lower inductance, whileother pathways may be electrically coupled to an energy source or anenergy load. A pathway of a second plurality of pathways may have alower impedance operable for portions of energy to be taken away fromeither of the same at least one energy source or at least one energyload of the circuit assembly. This same pathway of low impedance may notbe electrically directly coupled to either the same at least one energysource or at least one energy load of the circuit assembly as the onepathway of lower inductance. A system may have both a pathway of leastinductance and a pathway of least impedance which are not the samepathway.

[0039] In contrast to capacitors found in the industry wherein anequivalent series inductance (ESL) of a capacitor device is normallysize dependant, in the present invention the pathway of least impedanceand the pathway of least inductance for a circuit for energyconditioning may be achieved independent of the physical size of thedevice. These aspects depend on a predetermined capacitance developed bya predetermined layers in the present invention.

[0040] Arranging the pathways allows the resistance of the conductivematerial of the pathways to primarily determine the energy delivery, orrelative efficiency or effect between at least one source of energy andone energy utilizing load of an integrated circuit, for example. The ESLmay be a negligible factor, rather than a primary factor for deliveryoutcome or decoupling void of debilitating inductances.

[0041] In an illustrative pathway arrangement illustrated in FIGS. 1A,1B, 1C, 5A and 5B, wherein the various propagating energies may becomplementary, the pathway arrangement, upon placement into a circuitarrangement, may allow for energy propagation within or along certainenergy pathways of the pathway arrangement, thereby allowing for themutual interaction of opposite portions of pathway-soured magneticfields produced by the propagation of energy field currents emanatingoutwardly from each set of the complementary conductors. This mutualinteraction maybe a mutual cancellation in embodiments wherein certainpathways may be partially or totally physically shielded from othercomplementary pathways, and may be placed within an influencing distanceof those other complementary pathways. Further, a substantial similarityin size and shape of the respective complementary pathways, includingthe spaced-apart relationship and the interpositioning of a shieldingbetween pathways, and the conductively isolated relationship of thepathways, may contribute to this mutual cancellation effect.Additionally, the shielding operations may be predicated on a relativepositioning of a mating of the paired pathways relative to theconductive electrostatic shielding. At least the complementary energyconditioning functions and electrostatic shielding dynamics discussedherein may operate on various energy propagating in various directionsalong various predetermined pathways, and may operate on circuits havingdynamic operation utilizing the pathway arrangement.

[0042] A sub-combination of electromagnetically/electrostaticallyactuated impedance states may develop along or within a pathwayarrangement, or along or within a closely coupled external conductiveportion conductively coupled to separate or multiple groupings ofshields, to thereby form an energy conditioning circuit. Theseelectromagnetically/electrostatically actuated impedance states maydevelop, for example, because of the energization of one paired set ofpathways of one circuit portion, but not necessarily develop on anotherpaired set of pathways from another circuit portion, for example.

[0043] According to an aspect of the present invention, each shield mayinclude a main-body 81. Main-bodies 81 may collectively and conductivelycouple to one another and at the same time may substantially immure andshield the main-body 80 of the energy pathways. In other embodiments ofthe present invention, the collective shielding main-body 81 may onlypartially immure or shield the pathway main-body 80 s in at least oneportion of the shielding.

[0044] According to an aspect of the present invention, a balanced,symmetrical, pathway arrangement may result from the symmetry of certainsuperposed shields, from complementary pathway sizing and shaping,and/or from reciprocal positioning and pairing of the complementarypathways. Manufacturable balanced or symmetrical physical arrangementsof pathways, wherein dynamic energy propagation, interactions, pairingsor match-ups of various dynamic quantities occur, may operate at lessthan a fundamental limit of accuracy of testing equipment. Thus, whenportions of these complementary energy quantities interactsimultaneously, the energy may be beyond the quantifiable range of thetypical testing equipment. Thus, the extent to which the measurement maybe obtained may employ increased controllability, and thereby theelectrical characteristics and the effect on electrical characteristicsmay be controlled, such as by predetermining the desired measurability,behavior or enhancement to be provided, and by a correspondentarrangement of the elements, such as specifically by an arrangement ofthe elements to provide the desired measurability or effect. Forexample, a desired electrical characteristic may be predetermined for adesired enhancement by varying at least a portion of the complementarybalance, size, shape, and symmetry of at least one pathway paring, asset forth herein below and as illustrated in FIGS. 1A, 1B, 1C, 5A and5B, for example.

[0045] Thus, the extent of energy interactions, mutual energypropagation timings and interferences, for example, may be controlled bytolerances within the pathway arrangement. A manufacturing process, orcomputer tolerance control, such as semiconductor process control, maycontrol these tolerances, for example. Thus, the pathways of anembodiment may be formed using manufacturing processes, such as passivedevice processes, apparent to those skilled in the art. Mutual energypropagation measurements may thereby be cancelled or suppressed by theformation, and process of formation, of the pathway arrangement.

[0046] A pathway arrangement may, as set forth hereinabove, include asequentially to positioned grouping of pathways in an amalgamatedelectronic structure having balanced groupings of pathways. The balancedgrouping may include a predetermined pathway architecture having astacked hierarchy of pathways that are symmetrical and complementary innumber, and that are positioned complementary to one another, therebyforming pairs, each of which pair is substantially equidistant from eachside of a centrally positioned shield, wherein each shield may provide asymmetrical balancing point for both each pair pathway and the overallpathway hierarchy as depicted in FIGS. 1A to 41, for example. Thus,predetermined identically sized, shaped and complementary positionedpathways may be present on either side of a centrally positioned shieldfor each separate circuit portion. A total circuit may have itscomplementary portions symmetrically divided into a complementaryphysical format including a reverse-mirror image positioning of pairedshielded, complementary sized and shaped pathways, sandwiching at leastone interposing shield.

[0047] According to an aspect of the present invention, each pathway maybe, for example, a first interconnect substrate wrapping around, orholding, an integrated circuit wafer, a deposit, an etching, or aresultant of a doping process, and the shield may be, for example, apathway 55 substrate, an energy conditioning embodiment or energyconditioning substrate, a deposit, an etching, a resultant of a dopingprocess, and may have, for example, resistive properties.

[0048] Additional elements may be utilized, including conductive andnonconductive elements, between the various pathways. These additionalelements may take the form of ferromagnetic materials orferromagnetic-like dielectric layers, and/or inductive-ferrite 60dielectric derivative materials. Additional pathway structural elementsmay be utilized, including conductive and nonconductive multiplepathways of different conductive material compositions, conductivemagnetic field-influencing material hybrids and conductive polymersheets, various processed conductive and nonconductive laminates,straight conductive deposits, multiple shielding pathway pathwaysutilizing various types of magnetic material shields and selectiveshielding, and conductively doped and conductively deposited on thematerials and termination solder, for example, in addition to variouscombinations of material and structural elements, to provide a host ofenergy conditioning options.

[0049] Non-conductor materials may also provide structural support ofthe various pathways, and these non-conductor materials may aid theoverall energized circuit in maintaining the simultaneous, constant anduninterrupted energy propagation moving along the pathways. Dielectricmaterials for example, may include one or more layers of materialelements compatible with available processing technology. Thesedielectric materials may be a semiconductor material such as silicon,germanium, gallium arsenide, or a semi-insulating and insulatingmaterial such as, but not limited to any K, high K and low Kdielectrics.

[0050] Pathway and conductor materials may be selected from a groupconsisting of Ag, Ag/Pd, Cu, Ni, Pt, Au, Pd and other such conductivematerials and metals. Combinations of these metal materials are suitablefor the purposes discussed herein, and may include appropriate metaloxides, such as ruthenium oxide, which, depending on the exigencies of aparticular application, may be diluted with a suitable metal. Otherpathways may be formed of a substantially non-resistive conductivematerial. Any substances and processes that may create pathways fromconductive, non-conductive, semi-conductive material, and/or Mylar filmsprinted circuit board materials, or any substances or processes that maycreate conductive areas such as doped polysilicons, sinteredpolycrystallines, metals, polysilicon silicates, or polysilicon silicidemay be used within or with the pathway arrangement.

[0051] An exemplary embodiment of the present invention may utilize aninternal shield structural architecture to insure energy balancingconfigurations within the various arrangements, rather than a specificexternal circuit balance. This balancing configuration is dependent uponthe relative positioning of all the shields in relationship to theshared and centrally positioned shield, and the actual paired shieldspositioned in specific quantities, to simultaneously provide shieldingfor the electrically opposing shielded paired pathways utilized bypropagating energy. This allows these electrically opposingcomplementary pathways to be located both electrically and physically onthe opposite sides of the centrally positioned and shared commonconductive shield. This interposition of the central and shared shieldsmay create a voltage divider that divides various circuit voltages inhalf and that provides, to each of the oppositely paired shieldedconductors, one half of the voltage energy normally expected. Theenergized circuitry, including shielded conductors, may be balancedelectrically or in a charge-opposing manner and with respect to acentrally positioned shield, to a common and shared pathway, or to eachrespective, isolated circuit system portion. Each common circuit memberof an isolated circuit system may be attached or coupled to a commonarea or common pathway, thereby providing an external common zerovoltage. Thus, the embodiment may have multiple sets of shieldselectrically or physically located between at least one of the variouselectrically or charge opposing, shielded pairs or grouped complementarypairs of pathways in an interposed shielding relationship, supportedwith additional outer sandwiching shields, designated herein as -IM thatare additionally coupled and, in part, form the shielding structure.

[0052] An exemplary embodiment may also be placed into one or moreenergy circuits that utilize different energy sources and that maysupply one or more separate and distinct energy-utilizing loads. Whenenergized for multiple energy conditioning operations and for providingsimultaneous and effective energy conditioning functions, such aselectromagnetic interference filtering, suppression, energy decouplingand energy surge protection, each separate and distinct circuit isutilizing the multiple commonly shared universal shield structure andcircuit reference image, or node.

[0053] According to an aspect of the present invention,energy-conditioning functions may maintain an apparent balanced energyvoltage reference and energy supply for each respective energy-utilizingload within a circuit. This energized arrangement may allow for specificenergy propagation utilizing a single, or multiple, isolated pathwayarrangement, and may not require balancing on a single, centralizedshield. A shield may be physically and electrically located between oneor multiple energy sources and one or multiple energy utilizing loads,depending upon the number of separate and isolated pathways. Thusshielding relative, centralized pathways may be in both co-planar andstacked variants of exemplary embodiment.

[0054] When the internally positioned paired shielded pathways aresubsequently attached, or conductively coupled, to externallymanufactured pathways, the internally positioned paired shields may besubstantially enveloped within the cage-like shield structure, therebyminimizing internally generated energy strays and parasitics that maynormally escape or couple to an adjacent shielded pathway. Theseshielding modes utilize propagating energy to the various pathways andmay be separate of the electrostatic shield effect created by theenergization of the shield structure. The propagating energy propagatingin a complementary manner provides energy fields of mutually opposed,mutually cancelled fields as a result of the close proximity of oppositepropagation. The complementary and paired pathways may provide aninternally balanced opposing resistance load function.

[0055] A device according to an aspect of the present invention maymimic the functionality of at least one electrostatically shieldedtransformer. Transformers may be widely used to provide common modeisolation dependent upon a differential mode transfer across the inputsin order to magnetically link the primary windings to the secondarywindings to transfer energy. As a result, common mode voltage across theprimary winding is rejected. One flaw inherent in the manufacturing oftransformers is the propagating energy source capacitance between theprimary and secondary windings. As the frequency of the circuitincreases, so does capacitive coupling, until circuit isolation may becompromised. If enough parasitic capacitance exists, high frequency RFenergy may pass through the transformer and cause an upset in thecircuits on the other side of the isolation gap subjected to thetransient event. A shield may be provided between the primary andsecondary windings by coupling to a common pathway reference sourcedesigned to prevent capacitive coupling between the multiple sets ofwindings. A device according to an aspect of the present inventionimproves upon, and reduces the need for, transformers in circuits. Thedevice may use a physical and relative, common pathway shield tosuppress parasitics and also may use relative positioning of commonpathway shields, a complementary paired pathway layering, the variouscouplings of the pathway layering, and an external conductive couplingto a conductive area per isolated circuit system, in combination withthe various external circuitry, to effectively function as atransformer. If an isolated circuit system is upset by transients, theelectrostatically shielded, transformer function of the device discussedherein may be effective for transient suppression and protection, andmay simultaneously operate as a combined differential mode and commonmode filter. Each set of relative shields and relative conductors may beconductively coupled to at least the same external pathway to provide atransformer functionality for example,

[0056] Propagated electromagnetic interference may be the product ofboth electric and magnetic fields. A device according to an aspect ofthe present invention may be capable of conditioning energy that usesDC, AC, and AC/DC hybrid-type propagation, including conditioning energyin systems that may contain different types of energy propagationformats and in systems that may contain more than one circuitpropagation characteristic.

[0057] In an exemplary embodiment, perimeter conductive couplingmaterial for coupling or connecting, by conductive joining, of externalportions of a typical embodiment into an assembly may be accomplished byconductive or non-conductive attachments to various types of angled,parallel or perpendicular, as those terms apply relative to at leastanother pathway, conductors known as apertures or blind or non-blindVIAs, passing through, or almost through, portions respectively of anexemplary embodiment. Couplings to at least one or more load(s), such asa portion of an integrated circuit, for one aspect of the invention mayinvolve a selective coupling, or not, to these various types ofconductors, such as apertures and VIAs.

[0058] Fabricating a pathway may include forming one or more platedthrough hole (PTH) via(s) through one or more levels of a pathway.Electronic packages commonly include multiple interconnect levels. Insuch a package, the invention may include layerings of patternedconductive material on one interconnect level that may be electricallyinsulated from patterned conductive material on another interconnectlevel, such as by dielectric material layers.

[0059] Connections or couplings between the conductive material at thevarious interconnect levels may be made by forming openings, referred toherein as vias or apertures, in the insulating portions or layers, thatin turn can provide an electrically conductive structure such that thepatterned or shaped conductive material portions or pathways fromdifferent levels are brought into electrical contact with each other.These structures can extend through one or more of the interconnectlevels. Use of conductive, non-conductive or conductively-filledapertures and VIAs allows propagating energy to transverse an exemplaryembodiment as if utilizing a by-pass or feed-through pathwayconfiguration of an embodiment. An embodiment may serve as a support, asystem or a subsystem platform that may contain both or either activeand passive components layered to provide the benefits described forconditioning propagated energy between at least one source and at leastone load.

[0060] An aspect of the present invention may provide a conductivearchitecture or structure suitable for inclusion in a packaging or anintegrated circuit package having other elements. Other elements may bedirectly coupled to the device for simultaneous physical and electricalshielding by allowing simultaneous energy interactions to take placebetween grouped and energized complementary conductors that are fed byother pathways. Typical capacitive balances found between at least oneshielding pathway may be found when measuring opposite sides of theshared shield structure per isolated circuit, and may be maintained atmeasured capacitive levels within this isolated circuit portion, evenwith the use of common non-specialized dielectrics or pathway conductivematerials. Thus, complementary capacitive balancing, or tolerancebalancing characteristics, of this type of electrical circuit due toelement positioning, size, separations and attachment positioning allowan exemplary embodiment having an isolated circuit system manufacturedat 3% capacitive tolerance, internally, to pass to a conductivelycoupled and energized isolated circuit system a maintained andcorrelated 3% capacitive tolerance between electrically opposing andpaired complementary pathways of each respective isolated circuitsystem, with respect to the dividing shield structures placed into theisolated circuit system.

[0061] An exemplary embodiment may allow utilization of relativelyinexpensive dielectrics, conductive materials and various other materialelements in a wide variety of ways. Due to the nature of thearchitecture, the physical and electrical dividing structure created mayallow the voltage dividing and balancing among the grouped, adjacentelements, and may allow for the minimization of the effect of materialhysteresis and piezoelectric phenomenon to such a degree thatpropagating energy normally disrupted or lost to these effects may beessentially retained in the form of active component switching responsetime, as well as instantaneous ability to appear to the variousenergy-utilizing loads as an apparent open energy flow simultaneously onboth electrical sides of a pathway connecting or coupling from an energysource to a respective load, and from the load back to the source.

[0062] A structured layer may be shaped, buried within, enveloped by, orinserted into various electrical systems and sub-systems to perform lineconditioning or decoupling, for example, and to aid in or to allow for amodifying of an electrical transmission of energy to a desired orpredetermined electrical characteristic. Expensive, specialized,dielectric materials that attempt to maintain specific or narrow energyconditioning or voltage balancing may no longer be needed for bypass,feed through, or energy decoupling operations for a circuit.

[0063] A device according to an aspect of the present invention may, asset forth hereinabove, be placed between each isolated circuit and apaired plurality of pathways or differential pathways. This exemplarydevice may operate effectively across a broad frequency range, ascompared to a single discrete capacitor or inductor component, and maycontinue to perform effectively within an isolated circuit systemoperating beyond, for example, a GHz.

[0064] As set forth hereinabove, the exemplary device may performshielding functions in this broad frequency range. A physical shieldingof paired, electrically opposing and adjacent complementary pathways mayresult from the size of the common pathways in relationship to the sizeof the complementary pathways, and from the energized, electrostaticsuppression or minimization of parasitics originating from thesandwiched complementary conductors and preventing external parasitics.Further, the positioning of the shielding, relative to shielding that ismore conductive, may be used to protect against inductive energy and“H-Field” coupling. This technique is known as mutual inductivecancellation.

[0065] Parasitic coupling is known as electric field coupling. Theshielding function discussed hereinabove provides primary shielding ofthe various shielded pathways electrostatically against electric fieldparasitics. Parasitic coupling involving the passage of interferingpropagating energy because of mutual or stray parasitic energyoriginating from the complementary conductor pathways may be therebysuppressed. A device according to an aspect of the present inventionmay, for example, block capacitive coupling by enveloping oppositelyphased conductors in the universal shield architecture with stackedconductive hierarchical progression, thereby providing an electrostaticor Faraday shield effect with respect to the pathway positioning as tothe respective layering and position, both vertically and horizontally,of the pathways. The shielding pathway architecture may be used tosuppress and prevent internal and external parasitic coupling betweenpotentially noisy conductors and victim conductors, such as by animposition of a number of common pathway layers that are larger than thesmaller paired complementary pathways, but that are positioned betweeneach of the complementary pathway conductor pairs to suppress and tocontain the stray parasitics.

[0066] Further, as set forth hereinabove, positioning of the shielding,relative to shielding that is more conductive, may be used againstinductive energy and “H-Field” coupling. This cancellation isaccomplished by physically shielding energy, while simultaneously usinga complementary and paired pathway positioned to allow for the insettingof the contained and paired complementary pathways within an area sizecorrespondent to the shield size. A device according to an aspect of thepresent invention is adapted to use shields separately as internalshields or groupings, thereby substantially isolating and sandwichingpairs of electrically opposing complementary pathways, and therebyproviding a physically tight or minimized energy and circuit looppropagation path between each shield and the active load. Closeproximity of shields and non-shields may allow energy along shields evenif a direct electrical isolation exists because of 801 material type orthe spacing. Flux cancellation of propagating energy along paired andelectrically opposing or differential pathways may result from spacingof pathways apart by a very small distance for oppositely phasedelectrically complementary operations, thereby resulting in asimultaneous stray parasitic suppression and containment functionattributable to tandem shielding, and thereby enhancing energyconditioning.

[0067] In attaining minimum areas for various current loops in anisolated circuit system, additional shielding energy currents may bedistributed around component shielding architectures. A plurality ofshields as described hereinabove may be electrically coupled as eitheran isolated circuit's reference node, or chassis ground, and may berelied on as a commonly used reference pathway for a circuit. Thus, thevarious groups of internally paired, complementary pathways may includepropagating energy originating from one or more energy sourcespropagating along external pathways coupled to the circuit by aconductive material. Energy may thus enter the device, undergoconditioning, and continue to each respective load.

[0068] The shielding structure may allow for a portion of a shield tooperate as the pathway of low impedance for dumping and suppressing, aswell as at least partially blocking return of unwanted electromagneticinterference noise and energy into each of the respective energizedcircuits. In an embodiment, internally located shields may beconductively coupled to a conductive area, thereby adaptively utilizingshielding structure for low impedance dumping and suppressing and atleast partially blocking return blocking of unwanted electromagneticinterference noise and energy. Additionally, another set of internallylocated shields may be conductively coupled to a second conductive area,thereby utilizing shields for low impedance dumping, suppressing and atleast partially blocking the return of unwanted electromagneticinterference noise and energy. The conductive areas may be electricallyor conductively isolated from one another.

[0069] Simultaneous suppression of energy parasitics may be attributedto the enveloping shielding pathway structure, in combination with thecancellation of mutually opposing energy fields, and may be furtherattributed to the electrically opposing shielded pathway pathways andpropagating energy along the various circuit pathways interacting withinthe various isolated circuits to undergo a conditioning effect takingplace upon the propagating energy. This conditioning may includeminimizing effects of H-field energy and E-field energy throughsimultaneous functions, such as through isolated circuits that containand maintain a defined electrical area adjacent to dynamic simultaneouslow and high impedance pathways of shielding in which various pairedpathways have their respective potentials respectively switching as aresult of a given potential located on a shielding and usedinstantaneously and oppositely by these pairings with respect to theutilization by energy found along paired routings of the low and highimpedance shields.

[0070] The various distance relationships created by the positionaloverlapping of energy routings within the isolated circuits combine withthe various dynamic energy movements to enhance and cancel the variousdegrees of detrimental energy disruptions normally occurring withinactive components or loads. The efficient energy conditioning functionsoccurring within the passive layering architecture allow for developmentof a dynamic “0” impedance energy “black hole”, or energy drain, along athird pathway coupled common to both complementary pathways and adaptedto allow energy to be contained and dissipated upon the shielding,within the various isolated circuits and attached or conductivelycoupled circuits. Thus, electrically opposing energies may be separatedby dielectric material and/or by an interposition shield structure,thereby allowing dynamic and close distance relationship within aspecific circuit architecture, and thereby taking advantage ofpropagating energy and relative distances to allow for exploitation ofmutual enhancing cancellation phenomenon and an electrostaticsuppression phenomenon to, exponentially allow layered conductive anddielectric elements to become highly efficient in energy handlingability.

[0071] According to an aspect of the present invention, a device mayutilize a single low impedance pathway or a common low impedance pathwayas a voltage reference, while utilizing a circuit maintained andbalanced within a relative electrical reference point, therebymaintaining minimal parasitic contribution and disruptive energyparasitics in the isolated circuit system. The various attachmentschemes described herein may allow a “0” voltage reference, as discussedhereinabove, to develop with respect to each pair or plurality of pairedcomplementary conductors located on opposite sides of the shared centralshield, thereby allowing a voltage to be maintained and balanced, evenwith multiple Simultaneous Switching Operations states among transistorgates located within an active integrated circuit, with minimaldisruptive energy parasitics in an isolated circuit.

[0072] Shields may be joined using principals of a cage-like conductiveshield structure to create one or more shieldings. The conductivecoupling of shields together with a larger external conductive area maysuppress radiated electromagnetic emissions and as a larger areaprovides a greater conductive area in which dissipation of voltages andsurges may occur. One or more of a plurality of conductive or dielectricmaterials having different electrical characteristics may be maintainedbetween shields. A specific complementary pathway may include aplurality of commonly conductive structures performing differentiallyphased conditioning with respect to a “mate”, or paired, plurality ofoppositely phased or charged structures forming half of the total sum ofmanufactured complementary pathways, wherein one half of thecomplementary pathways forms a first plurality of pathways, and whereinthe second half forms a second plurality of pathways. The sum of thecomplementary pathways of the first and the second plurality of pathwaysmay be evenly separated electrically, with an equal number of pathwaysused simultaneously, but with half the total sum of the individualcomplementary pathways operating from, for example, a range of 1 degreeto approximately 180 degrees electrically out of phase from theoppositely positioned groupings. Small amounts of dielectric material,such as microns or less, may be used as the conductive materialseparation between pathways, in addition to the interposing shield,which dielectric may not directly physically or conductively couple toany of the complementarily operating shielded pathways.

[0073] An external ground area may couple or conductively connect as analternative common pathway. Additional numbers of paired externalpathways may be attached to lower the circuit impedance. This lowimpedance phenomenon may occur using alternative or auxiliary circuitreturn pathways.

[0074] A shield architecture may allow shields to be joined together,thereby facilitating energy propagation along a newly developed lowimpedance pathway, and thereby allowing unwanted electromagneticinterference or noise to move to this created low impedance pathway.

[0075] Referring now to FIG. 1A through FIG. 5B, which generally showvarious common principals of both common and individual variants of anexemplary embodiment configured in a co-planar variant (FIGS. 1A-4I) anda stacked variant (FIGS. 5A and 5B).

[0076] In FIG. 1A, there are shown relative locations of the variouspathway extensions disclosed according to an aspect of the presentinvention. A portion of a relative balanced andcomplementary-symmetrical arrangement utilizing a center shieldingpathway designated 8“XX”-“X”M is adapted in the arrangement as thefulcrum of balanced conductive portions in a co-planar variant. Apathway arrangement including at least a first and a second plurality ofpathways, wherein the first plurality has at least one pair of pathwaysarranged electrically isolated from each other and orientated in a firstcomplementary relationship, is illustrated. Additionally, at least afirst half of the second plurality is arranged electrically isolatedfrom a second half of the second plurality, wherein at least twopathways of the second plurality are electrically isolated from thepathways of first plurality. The pathway arrangement may also include amaterial having properties, such as dielectric, ferromagnetic, orvaristor for example, spacing apart pathways of the pathway arrangement.The pathways of the first half of the second plurality are electricallycoupled to one another, and the pathways of the second half of thesecond plurality are electrically coupled to one another. A total numberof pathways of the first half of the second plurality may be an oddnumber greater than one, and a total number of pathways of a second halfof the second plurality may also be an odd number greater than one.According to an aspect of the present invention, the pathways of thefirst half of the second plurality are positioned in a first superposedalignment, while the pathways of the second half of the second pluralityare positioned in a second superposed alignment, with the first andsecond superposed alignments in a mutual superposed alignment hereindefined as a co-planar arrangement.

[0077] In a non co-planar arrangement, the pathways of the first half ofthe second plurality may be positioned in a first superposed alignment,and the pathways of the second half of the second plurality may bepositioned in a second superposed alignment, with the first and secondsuperposed alignments in arrangement one atop the other. In onearrangement, at least four pathways are electrically isolated.

[0078] An illustrative embodiment of the present invention may includeat least three pluralities of pathways, including a first plurality ofpathways and a second plurality of pathways. The first and secondpluralities of pathways may include pathway members of the firstplurality having an equal and opposite pathway member found in thesecond plurality of pathways. Members of the first and secondpluralities of pathways may be substantially the same size and shape,and may be positioned complementary, and may also operate in anelectrically complementary manner. Thus, the pairings of the first andsecond pluralities of pathways may result in identical numbers ofmembers of the first and second pluralities of pathways. An exemplaryembodiment may provide at least a first and a second shield allowing fordevelopment of individual isolated low circuit impedance pathways.Structurally, the shields may be accomplished by a third plurality ofpathways and a fourth plurality of pathways. Each shielding pluralitymay include shields of equal size and shape. Each of the third andfourth plurality of pathways may be conductively coupled. Conductivecoupling may be accomplished by a variety of methods and materials knownto those possessing an ordinary skill in the pertinent arts. Thus, whenthe third and a fourth plurality are grouped as two sets of shieldsutilizing the first and second plurality receiving shielding, the thirdand fourth pluralities may be coupled to a common pathway to develop alow circuit impedance pathway for energy propagation for conditioning ofthe circuit energy.

[0079] Pathways may additionally be arranged in a bypass arrangement,such that when placed face to face, main-body pathways 80 may be alignedsuperposed, with the exception of any pathway extensions such as 812NNE,81NNE, 812SSW and 811SSW of the lower sub-circuit portion, for example,shown as mirror images depicted in FIG. 5A and FIG. 5B, for example.

[0080] Within the pluralities, individual pathway members may be ofsubstantially the same size and shape and may be conductively coupled.However, individual pathway members of one plurality may not beconductively coupled to members of a different plurality of pathways.There may be situations wherein members of one plurality may beconnected to members of a different plurality, such as wherein a firstplurality of shields and a second plurality of shields are externallycoupled to the same conductor.

[0081] Common elements may include energy flow in accordance withconceptual energy indicators 600, 601, 602, 603 depicting the dynamicenergy movements in co-planar shielded by-pass pathways, such as thoseshown in FIG. 1A-1C. An embodiment may provide for at least multipleshields for development of multiple isolated low circuit impedancepathways for multiple circuits.

[0082] Referring still to FIG. 1A, pathways may be shielded by therelative, common pathways, and may include a main-body pathway 80 withat least one pathway extension 812“X”. The shields shown include amain-body shield pathway 81 with at least one pathway extensiondesignated 99“X”/79“X”. The shields may sandwich and envelope themain-body 799, including a conductive inner pathway formed of conductivematerials from the family of noble or base metals traditionally used inco-fired electronic components or conductive material, such as Ag,Ag/Pd, Cu, Ni, Pt, Au, Pd, or combination materials such as metal oxideand glass frit. A capacitance and a resistance value may be achieved inone family of pathways, as described hereinabove, such as by use ofruthenium oxide as the resistive material and Ag/Pd as the conductivematerial. Further, variations in pathway geometry may yield differentresistance and capacitance values. Variations may be achieved byaltering the materials from which the pathways are made. For example, aconductive metal, such as silver, may be selectively added to the metaloxide/glass frit material to lower the resistance of the material.

[0083] A plurality of pathways, 865-1 and 865-2, are shown positionedco-planar and spaced apart on a same portion of material 801. Eachpathway of the co-planar pathways 865-1 and 865-2, may be formed ofconductive material 799, or a hybrid of conductive material and anothermaterial, herein designated as 799“x”. Each co planar pathway 865-1 and865-2 may also be formed as a bypass pathway, wherein each pathwayincludes a main-body pathway 80 having a corresponding main-body edgeand perimeter, 803A and 803B, respectively and at least one pathwaycontiguous extension 812“X”. Each co-planar pathway 865-1 and 865-2, mayinclude at least one pathway contiguous extension 812SSW and 811SSW witha portion of the main-body edge 803A and 803B extending therefrom.Extension 812“X” is a portion of the pathway material formed inconjunction with a main-body pathway 80 from which it extends. Main-bodypathway 80, an 812“X” may be found as an extension of material 799 or799“x” extending beyond an accepted average perimeter edge 803“X”.Extensions 812“X” and 79“X” may be found respectively positioned as acontiguous portion of the pathway from which it is formed. Eachmain-body pathway may have edge 803A, 803B positioned relative andspaced apart a distance 814F from the embodiment edge 817. Embodimentedge 817 may include a material 801. Co-planar main-body pathway's edge803“x” may be positioned and spaced apart a distance 814J. Pathwayextensions 812SSW and 811SSW may conductively couple a respectivepathway main-body 80 to an outer pathway 890SSW and 891SSW, which may bepositioned at edge 817. The co-planar arranged, main-body pathway 80 maybe positioned “sandwiched” between the area of registered coverage oftwo layering of co-planar, main-body pathway 81 s.

[0084] Combining mutually opposing fields causes a cancellation orminimization effect. The closer the complementary, symmetricallyoriented shields, the better the resulting mutually opposingcancellation effect on opposing energy propagation. The more superposedthe orientation of the complementary, symmetrically oriented shields is,the better the resulting suppression of parasitics and cancellationeffect.

[0085] Referring still to FIG. 1A, the edges of the plurality ofco-planar shields may be represented by dotted lines 805A and 805B.Main-body pathways 81 of each of the plurality of shields are largerthan a sandwiching main-body pathway 80 of any corresponding sandwichedpathway. This may create an inset area 806 relative to the positions ofthe shields and remaining pathways. The size of main-bodies 80 and 81may be substantially similar, and thus the insetting positioningrelationships may be minimal in certain embodiments. Increased parasiticsuppression may be obtained by insetting pathways, including a main-body80, to be shielded by larger pathway main-body 81 s. For example, aninset of a main-body 80 of pathways 865-1 inset may be separated adistance of 1 to 20+32 times the spacing provided by the thickness ofthe material 801 separating pathway 865-1 and adjacent center co-planarpathway 800-IM-1, as illustrated in FIG. 1B.

[0086] Plurality of co-planar shield edges 805A and 805B may bepositioned and spaced apart a distance 814K, and may be a distance 814relative to edges 805A and 805B and the edge 817. Other distances 814Jrelative from either edges 803A and 803B may be provided.

[0087] Further, distance 814F may be present between one 803“X” and anedge 817. Each co-planar shield may include a plurality of contiguouspathway extension portions, such as, for example, portions 79NNE, 79SSE,99NNE and 99SSE, extending from the plurality of co-planar shield edges805A and 805B. Plurality of co-planar shields may include a plurality ofouter pathway material 901NNE, 901SSE, 902NNE and 902SSE positioned atthe edge 817. Conceptual energy indicators 602 represent the variousdynamic energy movements within ro the co-planar pathways 865-1 and865-2. Unwanted energy may be transferred to the co-planar shields inaccordance with the provision by the shields providing for a lowimpedance pathway, which shields may additionally be electricallycoupled to another pathway or conductive area.

[0088] Referring now to FIGS. 1B and 1C, layer sequences are illustratedfor a first plurality of co-planar pathways 865-1, 865-2, a secondplurality of co-planar pathways 855-1, 855-2, and a third plurality ofco-planer pathways 825-1-IM, 825-2-IM, 815-1, 815-2, 800-1-IM, 800-2-IM,810-1, 810-2, and 820-1-IM, 820-2-IM. The first, second, and thirdpluralities may be stacked to form an embodiment 3199, 3200, 3201. Thethird plurality of co-planar pathways may provide shielding. Main-bodies81 of the plurality of co-planer shields 825-1-IM, 825-2-IM; 815-1,815-2; 800-1-IM, 800-2-IM; 810-1, 810-2; and 820-1-IM, 820-2-IM may besubstantially similar in size and shape, and may be spaced apart inco-planar locations on different layers of material 801. The firstplurality of co-planar pathways 865-1 and 865-2 may have at least thecorresponding, opposing, and complementary second plurality of co-planarpathways 855-1 and 855-2. These first and second pluralities ofco-planar pathways, when oriented face to face, may have main-bodypathways 80 s co-registered and aligned except for the variouscontiguous pathway extensions 812“X”, 811“X”. As shown in FIGS. 1B and1C, a pair of outer co-planar pathways 820-1-IM, 825-1-IM may serve aspathway shields, thereby improving the shielding effectiveness of theother conductively coupled pluralities of pathways with a main-body 81s.

[0089] As illustrated in the varied embodiments 3199, 3200, 3201, thelocation of extensions 79NNE, 79SSE, of shields 825-1-IM, 815-1,800-1-IM, 810-1, and 820-1-IM and extensions 99NNE, 99SSE of the shields825-2-IM, 815-2, 800-2-IM, 810-2, and 820-2-IM, may be varied. In FIG.1B, for example, extensions 79NNE and 99NNE may be arranged spacedapart, diagonally from extensions 79SSE and 99SSE and on opposite sidesof shield main-body 81. In FIG. 1C, for example, extensions 79NNE and99NNE may be arranged spaced apart in line with extensions 79SSE and99SSE on opposite sides of shield main-body 81. In FIG. 1B, extensions812NNE and 811NNE may be arranged spaced apart, extending toward thesame edge 812 of layer of material 801, and extensions 812SSW and 811SSWmay be arranged spaced apart, each extending toward the opposite edge812 of layer of material 801. In FIG. 1C, pathways 865-1 and 865-2 maybe mirror images, as discussed hereinabove. Comparably to FIG. 1B,extensions 812NNE and 811NNE may be arranged spaced apart, extendingtoward opposite edges 817 of layer of material 801. Extensions 812SSWand 811SSW may be arranged spaced apart, extending toward the oppositeedge of layer of material 801, such that extensions 812NNE and 811SSWextend toward opposite edges 812“X” of the respective layer of material801.

[0090] Referring now to FIGS. 2A and 2B, FIG. 2A illustrates a schematicplan view of a an embodiment of FIG. 2B according to an aspect of thepresent invention. FIG. 2B depicts a pathway arrangement including alayout of a first, a second, a third, a fourth, a fifth, a sixth, aseventh, a eighth, a ninth and a tenth pathway, wherein at least thethird and the fourth pathway, for example, may be co-planar and arrangedspaced apart from each other. FIG. 2B illustrates the first and thesecond pathway arranged below the third and the fourth pathway, and thefifth and the sixth pathway arranged above the third and the fourthpathway, and the seventh and the eighth pathway arranged above the fifthand the sixth pathway, and the ninth and the tenth pathway, arrangedabove the seventh and the eighth pathway. These pathways have variousrespective internal contiguous pathway extensions 812“X”, 811“X”, 79“X”and 99“X”, and may be discrete components having the same minimalnumbers of layering. Internal contiguous pathway extensions 812“X”,811“X”, 79“X” and 99“X”, and conductively coupled external pathways890“X”, 891“X” 802“X” and 902“X”, may be coupled to the inner pathway ofthe plurality of co-planar pathways of the main-body pathway 80 and 81.

[0091] Referring now to FIGS. 3A and 3B, in FIG. 3A there is shown aschematic plan view of an embodiment of FIG. 3B, wherein outer pathwaysmay be selectively conductively coupled in at least two isolated circuitportions. FIG. 3B depicts an pathway arrangement including a minimallayout of a first, a second, a third, a fourth, a fifth, a sixth, aseventh, a eighth, a ninth and a tenth pathway, wherein at least thethird and the fourth pathway, for example, are co-planar and arrangedspaced apart from each other. The device shown in FIG. 3B may have thefirst and the second pathway arranged below the third and the fourthpathway, and the fifth and the sixth pathway arranged above the thirdand the fourth pathway, and the seventh and the eighth pathway arrangedabove the fifth and the sixth pathway, and the ninth and the tenthpathway arranged above the seventh and the eighth pathway. Thesepathways have various respective internal contiguous pathway extensions812“X”, 811“X-”, 79“X” and 99“X”, and may be discrete components havingthe same minimal number of layering.

[0092] Referring now to FIG. 3C, a plan view of a shield according to anaspect of the present invention is illustrated. The embodiment depictedin FIG. 3C includes at least one additional pathway, as compared to thedevice of FIG. 3B. This additional pathway 1100-IM“X” may be one of atleast a plurality of shields in the stack of pathways, which shields mayspan across the two circuit portions. Pathway 1100-IM“X” may be one ofat least two outer sandwiching shields in the stack of pathways. Shieldsmay span across the two circuits by adding a centrally arranged100-IM“X” pathway electrically coupled to the outer 1100-IM“X” shields.Pathways 1100-IM“X” may have at least one extension, and are illustratedwith two extensions 1099NNE and 1099SSE, and may allow for sandwichingshields for all of the pathways within the present invention. At leastthree shields may be coupled together and may include a centering shielddividing an energy load or energy source of an isolated circuit ordividing two isolated circuits.

[0093] A shield 00GS may be electrically isolated from other shields andmay be arranged to effect an energy propagation of an isolated circuit.An isolated circuit may be sandwiched by a shield. A shield may beelectrically coupled to a conductive area that is isolated from anyother conductive areas thereby effecting an energy propagation.

[0094]FIGS. 4A-4I depict assembled components of various embodimentsaccording to aspects of the present invention. The arrangements of FIG.4A to FIG. 41 may include minimal layouts of a first, a second, a third,a fourth, a fifth, a sixth, a seventh, a eighth, a ninth and a tenthpathway, wherein at least the third and the fourth pathway, for example,are co-planar and arranged spaced apart from each other. The first andthe second pathway may be arranged below the third and the fourthpathway, and the fifth and the sixth pathway may be arranged above thethird and the fourth pathway, and the seventh and the eighth pathway maybe arranged above the fifth and the sixth pathway, and the ninth and thetenth pathway may be arranged above the seventh and the eighth pathway.These pathways have various respective internal contiguous pathwayextensions 812“X”, 811“X”, 79“X” and 99“X”, and may be an assembledfinal discrete component, for example.

[0095] Referring to FIG. 5A, there is shown a stacking of multiple,non-shared circuits ho including groups of pathways according to anaspect of the present invention. Included in FIG. 5A is a marker 1000showing a continuation of the stacking arrangement to the next column ofFIG. 5A. Conceptual energy indicators 600, 601, 602, 603 indicate energyflow. Material 799 may be deposited on material 801 for component 6900shields designated 815-1, 800-1, 810-1-IM, 815-2, 800-2-IM, and 810-2.Shields 810-A and 810-B are separated shields of at least part of anisolated circuit system. Shields 815-A and -B are separated shields ofat least part of an isolated circuit system. Shields 820-A and 820-B areseparated shields at least part of an isolated circuit system. Shields825-A and 825-B are separated shields at least part of an isolatedcircuit system. Conductors 855-1 and 855-2 are separated and shieldedpathways in bypass configuration. Conductors 865-1 and 865-2 areseparated 70 and shielded pathways in bypass configuration. In FIG. 5A,a pathway arrangement is depicted including at least six orientations ofpathways of two types of pathways, wherein each orientation of thepathways of the at least six orientations of pathways providesconductive isolation from the remaining orientations of pathways.

[0096] Referring to FIG. 5B, there is shown a stacked shield structureaccording to an aspect of the present invention. FIG. 5B depicts anembodiment similar to that of FIG. 5A, wherein two sets of 855“X” and865“X” pathways are omitted for purposes of clarity, and wherein theshields of FIG. 5A are oriented in flip-flop for each relative set of855“X” and 865“X” pathways. The 79“X” pathway extensions may be rotated90 degrees relative to the various pathway extensions 811“x” and 812“X”.A dynamic result of this configuration, as illustrated by the conceptualenergy indicators, may be enhanced by nulling the extensions of the twosets of 855“X” and 865“X” pathways of the two isolated circuits, and byrelatively positioning the shield of each isolated circuit pairing 855Aand 865A approximately 90 degrees null to the various pathway extensionsof 855B and 865B.

[0097] Referring to FIG. 5B, there is shown a stacked shield structureaccording to an aspect of the present invention. FIG. 5B depicts anembodiment similar to that of FIG. 5A, wherein two sets of 855“X” and865“X” pathways are omitted for purposes of clarity, and wherein theshields of FIG. 5A are oriented in flip-flop for each relative set of855“X” and 865“X” pathways. The 79“X” pathway extensions may be rotated90 degrees relative to the various pathway extensions 811 “x” and812“X”. A dynamic result of this configuration, as illustrated by theconceptual energy indicators, may be enhanced by nulling the extensionsof the two sets of 855“X” and 865“X” pathways of the two isolatedcircuits, and by relatively positioning the shield of each isolatedcircuit pairing 865B and 865A approximately 90 degrees null to thevarious pathway extensions of 865B and 865A.

[0098] As discussed hereinabove, in an embodiment of the presentinvention, multiple complementary or paired shielded pathways mayinclude the first and second pluralities of pathways. Energy may utilizethe various paired, feed-through or bypass pathway layers in a generallyparallel and even manner, for example. Pathway elements may includenon-insulated and conductive apertures, and conductive through-VIAs, toprovide propagating energy and maintain a generally non-parallel orperpendicular relationship, and additionally maintain a separateelectrical relationship with an adjoining circuit. These pathways maymaintain balance internally, and may facilitate an electrical oppositionalong opposing complementary pairings. This relationship amongcomplementary pairs of pathways may occur while the pathways and theenergy are undergoing an opposite operational usage within the shieldingstructure attached externally.

[0099] Referring now to FIG. 5C, there is shown a relative plan view ofa stacked multiple, non-shared circuit network having VIAs and includinggroups of pathways according to an aspect of the present invention. Thedevice according to an aspect of the present invention depicted in FIG.5C includes a hole-through energy conditioner. Hole-through energyconditioners may be formed such that many of the energy propagationprincipals disclosed herein are retained, including the use of multiplesets of shields for energy conditioning possessing. FIG. 5C, furtherdepicts null pathway sets with pathway arrangement 6969. Pathwayarrangement 6969 is similar to FIG. 5B, with the absence of pathwayextensions 79“X”, 811“x” and 812“X”, and with the substitution of8879“X”, 8811“X” and 8812“X” VIAs functioning from a different directionrelative to the main-body 80 and 81.

[0100] Referring still to FIG. 5C, during the manufacturing process,conductive holes 912, VIAS or conductive apertures may be used tointerconnect 8806 an integrated circuit, and may be formed through oneor more pathway layers using mechanical drilling, laser drilling,etching, punching, or other hole formation techniques. Each specificinterconnection 8806 may enable various pathways to be electricallyconnected or insulated. Each specific interconnection 8806 may extendthrough all layers of pathway arrangement 6969, or may be bounded aboveor below by one or more layers. Pathway arrangement 6969 may include anorganic substrate, such as an epoxy material, or patterned conductivematerial. If an organic substrate is used, for example, standard printedcircuit board materials such as FR-4 epoxy-glass, polymide-glass,benzocyclobutene, Teflon, other epoxy resins, or the like could be usedin various embodiments. In alternate embodiments, a pathway arrangementcould include an inorganic substance, such as ceramic, for example. Invarious embodiments, the thickness of the levels may be approximately10-1000 microns. Interconnections 8806 between the various conductivelayers may also be formed by selectively removing dielectric andconductive materials, thereby exposing the conductive material of thelower conductive layers 904, and by filling the holes so formed by theremoval with a conductive paste 799A or electrolytic plating 799B, forexample.

[0101] Interconnections 8806 may couple exposed conductive layers to arelative side of the pathway arrangement 6969. Interconnections 8806 maytake the form of pads or lands to which an integrated circuit may beattached, for example. Interconnections 8806 may be formed using knowntechniques, such as by filling the selectively removed portions ofdielectric with conductive paste, electrolytic plating,photolithography, or screen printing, for example. The resulting pathwayarrangement 6969 includes one or more layers of patterned conductivematerial 904, separated by non-conducting layers, and interconnected byinterconnects 8806. Different techniques may be used to interconnect andisolate the various layers of patterned conductive material 799. Forexample, rather than forming and selectively removing portions of thevarious conducting 799 and non-conducting layers 801, openings betweenthe various layers may be included by selectively adding the desiredportions of the conducting 799 and non-conducting layers 801. Removaltechniques, such as chemical mechanical planarization, may be used tophysically abrade away multiple layers of different types of conductingand non-conducting materials, resulting in the desired openings forvarious interconnects.

[0102] Pathway arrangement 6969 may be configured using amulti-aperture, multilayer energy conditioning pathway set, with asubstrate format adapted to condition propagating energy. Pathwayarrangement 6969 may condition propagating energy by utilizing acombined energy conditioning methodology of conductively filledapertures, known in the art as VIAs 8879“X”, 8811“X” and 8812“X”, incombination with a multi-layer common conductive Faraday cage-likeshielding technology with immured propagational pathways.

[0103] Interconnecting pathway arrangement and an IC may be achievedwith wire bonding interconnection, flip-chip ball-grid arrayinterconnections, microBall-grid interconnections, combinations thereof,or any other standard industry accepted methodologies. For example. a“flip chip” type of integrated circuit, meaning that the input/outputterminations as well as any other pathways on the chip may occur at anypoint on its surface. After the IC chip is prepared for attachment topathway arrangement 6969, the chip may be flipped over and attached, bysolder bumps or balls to matching pads on the top surface of pathwayarrangement 6969. Alternatively, an integrated circuit may be wirebonded by connecting input/output terminations to pathway arrangement6969 using bond wires to pads on the top surface of pathway arrangement6969.

[0104] The circuits within pathway arrangement 6969 may act as a sourceto load pathway arrangement requiring capacitance, noise suppression,and/or voltage dampening. This capacitance may be provided by formationof the capacitance developed and embedded within pathway arrangement6969. This capacitance may be coupled to the integrated circuit loadsusing a paired pathway and the shield, as described above. Additionalcapacitance may be provided to a circuit electrically coupled to anintegrated circuit to provide voltage dampening and noise suppression.Close proximity of off-chip energy sources may provide a capacitanceeach along the low inductance path to the load. Common shieldingpathways may be utilized as the “0” voltage circuit reference node forboth off-chip energy sources the common conductive interposer energypathway configurations.

[0105] Pathway arrangement 6969 may be connected to an integratedcircuit by commonly accepted industry connection methods and couplings799A and 799B, including Bumpless Build-Up Layer (BBUL) packaging. Thistechnology enables higher performance, thinner and lighter packages, andlowers power consumption. In a BBUL package, the silicon die or IC isembedded in a package with a pathway arrangement operable as a firstlevel interconnect. Thus, the BBUL package as a whole is not justattached to one surface of the IC. For example, electrical connectionsbetween the die and one or more of the various shields and the packagemay be made with copper lines, not necessarily C4 solder bumps. Thesefeatures combine to make the package thinner and lighter than other ICpackages, while delivering higher performance and reducing powerconsumption. BBUL may enhance the ability of a manufacturer to couplemultiple silicon components to pathway arrangement 6969. Shieldedpathways 8811, 8812, and 8879 may be electrically connected betweenrespective energy sources and respective load of the IC by commonindustry methodologies, thereby allowing for conditioning of propagatingenergy. Shields 8879 may conductively coupled to a shield including1055-2. A shield and its other conductive portions including 8811 and8812 may be electrically coupled to a respective complementary pathwaywhich poses no polarity charge of significance before hook-up, therebypreventing each layer 8811 and 8812 from changing energy propagationdirection functions, such preventing layer 8811 and 8812 from changingfrom input and output to output and input, respectively, as isunderstood by those possessing an ordinary skill in the pertinent arts.

[0106] For stacked variants depicted in FIGS. 5A, 5B and 5C, addingthree pathways 1100-IM-“X”, including one between 810-1 and 815-2,designated as 1100-IM-“C”, may bisect a balanced symmetry of the totalnumber of pathways located into equal numbers on opposite sides of1100-IM-“C”. The addition of 1100-IM-1 and 1100-IM-2, electricallycoupled to 1100-IM-C, creates a common or a shield structure (not allshown). Shields of a shield structure may be of substantially the samesize or not. Shields may or may not be physically isolated from anyother shields for any one or more embodiments of the present invention.Thus, shields may or may not be electrically or conductively isolatedfrom any other shields for any one or more embodiments of the presentinvention.

[0107] An odd number of shields may be coupled together thereby allowingformation of a common reference or node utilizing all other shields. Thenumber of shields 1100-IM-“X” is not confined to using extensions1099NNE and 1099SSE such as shield 00GS, as any number of extensions inalmost any direction may be used to facilitate a coupling. A relativebalanced and complementary-symmetrical arrangement may be formed withrespect to a center shield 8“XX” or shield 800/800-IM for a as thearrangement fulcrum of balanced conductive portions. At least a partialflux field cancellation of energy propagating along or between pairedand electrically opposing complementary pathways occurs in this balancedbut shifted embodiment. Further, simultaneous stray energy parasitics,complementary charged suppression, physical and electrical shieldingcontainment and a faraday effect may also occur. This result is achievedbecause the magnetic flux energies travel at least partially along theshield wherein the RF return path is parallel and adjacent to acorresponding pathway. Thus, the magnetic flux energy may be measured orobserved relative to a return

[0108] Shifted pathways may be in relative balance and complementarilyand symmetrically positioned with respect to center shields, such asshields 800/800-“X”-IM, and may include a relatively shifted, balanced,complementary, and symmetrical arrangement of predetermined shields andpathways complementarily sandwiched around a centrally positionedshield, such as 800/800-IM, for example.

[0109] The exemplary embodiments of FIGS. 1A, 1B, 1C, through FIG. 41,for example may include these ‘shifted’ embodiments. These shiftedembodiments may include a multiplicity of layers having a shielding, apathway, a shielding, an pathway, and a shielding. Each of thesemultiplicity of layers may be centered and complementary about a centershield 800/800-“X”-IM, such as for co-planar variants, and the entiremultiplicity of layers may be centered about a main center shield.Complementarity and balance may be maintained about the center shield,and the main center shield, although individual shields may be shiftedto create discrete imbalances as between a given matched pathway pair,for example. Shifting may expose a portion of at least one pathwayoutside the perimeter of the superposed shielding, thereby allowing forparasitics and thereby varying, for example, impedance characteristics.

[0110] For example, a given pathway may be shifted 5 points to the left.This shifting may be accounted for in the matched pairs about a centershield, and, consequently, either an adjacent matched pair pathway ofopposing polarity may be shifted 5 points, or 5 adjacent pathways ofopposite polarity may each shift 1 point, thereby maintainingcomplementarity and balance. Further, pathways may remain within theperimeter of the superposed shielding, and nonetheless be shiftedthereunder. Such a shifting under the shielding may, nonetheless, makedesirable a balancing. However, certain exemplary embodiments not shownmay include situations wherein pathways are pulled toward the center ofa shield, and remain under the shield evidencing differing electricalcharacteristics, such as inductive behavior, in a balanced or unbalancedstate.

[0111] Referring now to FIG. 6, there is shown a stacked multiplecircuit including embodiment 6900, conductive energy pathways, isolatedenergy sources, isolated energy-utilizing loads, and isolated commonconductive pathways. The conductive energy pathways may be conductivelycoupled to embodiment 6900 by a conductive coupling material, such as,for example, by a solder or industry equivalent. Vias 315, conductivepathways continuing below the surface of the substrate, may couple tothe conductive pathways, and may include conductive material that servesas a contiguous conductive pathway for propagating energies. Theisolated common conductive pathways may not be directly coupled to theisolated energy sources or the isolated energy-utilizing loads. Asdiscussed hereinabove, embodiment 6900 may include four pluralities ofpathways including electrodes and shields, with each pluralityelectrically isolated. The shields may be conductively coupled. Theconductively coupled shields may be externally coupled to an isolatedcommon conductive pathway, which is not directly conductively coupled tothe electrodes, using a conductive coupling material. As shown in FIG. 6an electrode, 815-1, 800-1-IM and 810-1, may be conductively coupled to802GA, 802 GB. A shield, 815-2, 800-2-IM, and 810-2, may be conductivelycoupled to 902GA and 902 GB. These couplings may not be conductivelycoupled to the first plurality of electrodes or the second plurality ofelectrodes. In this configuration, both isolated circuits may beutilizing the isolated and separate voltage references and an isolatedcommon impedance path such as REF 1 and REF 2 in FIG. 6.

[0112] Referring now to FIG. 7, there is shown a stacked co-planarmultiple circuit including embodiment 3210, conductive energy pathways,isolated energy sources, isolated energy-utilizing loads, and isolatedcommon conductive pathways. The conductive energy pathways may beconductively coupled to embodiment 3210 by a conductive couplingmaterial. Vias 315, conductive pathways continuing below the surface ofthe substrate, may couple to the conductive pathways and may includeconductive material that serves as a contiguous conductive pathway forpropagating energies. The isolated common conductive pathways may not bedirectly coupled to the isolated energy sources or the isolatedenergy-utilizing loads. As discussed hereinabove, embodiment 3210 mayinclude four pluralities of pathways including electrodes and shields,with each plurality electrically isolated. The conductively coupledshields may be externally coupled to an isolated common energy pathway,which is not directly conductively coupled to the first or the secondplurality of electrodes in this co-planar arrangement. A third pluralityof electrodes, 815-1, 800-1-IM and 810-1 may be conductively coupled to802GA, 802 GB, 815-2 and 800-2-IM, and also, may be conductively coupledto 902GA, 902 GB, and may not be conductively coupled to the firstplurality or the second plurality. In this configuration, both isolatedcircuits may be utilizing a separate and a respective isolated andseparate voltage reference and a separate and a respective isolatedimpedance path, a separate and a respective isolated common impedancepath and at least one separate and respective low inductance pathwaysuch as REF 1 and REF 2 in FIG. 7.

[0113] Referring now to FIG. 4A thru to FIG. 7, the terminationelectrodes 890A, 890B, and 891A, 891B, 802GA, 802 GB, and 902GA, 902 GB,may be monolithic or multi-layered. Termination electrodes 802GA, 802GB,902GA, 902 GB, may be located at other respective portions of a sinteredbody. Each main body electrode layers 81 or 80, and the associateelectrode extensions 99/79G “X” or 812“X”, may define an electrode whichextends to, and conductively couples to, the associated terminationelectrodes 802GA, 802GB, 902GA, 902GB and 890A, 890B, and 891A, 891B.

[0114] The present invention may be utilized for many energyconditioning functions that utilize commonly coupled shielding structureelement for emulating a center tap of resistor/voltage divider network.This resistor/voltage divider network may be normally constructed usinga ratio of various integrated circuit resistors. However, variousintegrated circuit resistors may be replaced by a device according to anaspect of the present invention, the device utilizing, for example,specific conductive/resistive materials 799A or naturally occurringresistance properties of pathway material 799, or utilizing a variedphysical layout. A voltage dividing function may be present as portionsof a common and shared pathway shield structure are utilized to define acommon voltage reference located at both respective sides of the commonpathway shield structure.

[0115] In embodiments, whether initially stacked vertically during amanufacturing process, or in combination with a co-planar pairings asdescribed hereinabove, the number of complementary pathways pairings maybe multiplied in a predetermined manner to create a number of pathwayelement combinations of a generally physically or electrically parallelnature.

[0116] Further, although not shown, a device of the present inventionmay be fabricated in silicon and directly incorporated into integratedcircuit microprocessor circuitry or microprocessor chip packaging. Anysuitable method for depositing electrically conductive materials may beused, such as plating, sputtering, vapor, electrical, screening,stenciling, vacuum, and chemical including chemical vapor deposition(CVD).

[0117] While certain embodiments have been herein described in positionas “upper” or “above”, or “lower” or “below”, or any other positional ordirectional description, it will be understood that these descriptionsare merely relative and are not intended to be limiting.

[0118] The present invention may be implemented in a number of differentembodiments, including a energy conditioning embodiment as an energyconditioner for an electronic assembly, an energy conditioningsubstrate, an integrated circuit package, an electronic assembly or anelectronic system in the form of a energy conditioning system, and maybe fabricated using various methods. Other embodiments will be readilyapparent to those of ordinary skill in the art.

1. A device, comprising: at least a first and a second plurality ofpathways; wherein said first plurality further comprises at least twopathways arranged electrically isolated from each other and orientatedin a first complementary relationship; wherein at least a first numberof pathways of said second plurality is arranged electrically isolatedfrom a second number of pathways of said second plurality; and whereinthe at least two pathways of said second plurality are electricallyisolated from said first plurality.
 2. The device of claim 1, wherein atleast two pathways of said first number of pathways of said secondplurality are electrically coupled to one another; and wherein at leasttwo pathways of said second number of pathways of said second pluralityare electrically coupled to one another.
 3. The device of claim 1,wherein said first number of pathways of said second plurality is an oddnumber greater than one; wherein said second number of pathways of saidsecond plurality is an odd number greater than one; wherein at least twopathways of said first number of pathways of said second plurality areelectrically coupled to one another; and wherein at least two pathwaysof said second number of pathways of said second plurality areelectrically coupled to one another.
 4. The device of claim 1, furthercomprising a spacing material that at least spaces apart two pathways ofsaid circuit.
 5. The device of claim 4, wherein said spacing materialcomprises a dielectric.
 6. The device of claim 1, wherein said firstnumber of pathways of said second plurality are in a first alignment;and wherein said second number of pathways of said second plurality arein a second alignment.
 7. The device of claim 1, wherein said firstnumber of pathways of said second plurality are in a first superposedalignment; and wherein said second number of pathways of said secondplurality are in a second superposed alignment.
 8. The device of claim6, wherein the first alignment and the second alignment are in asuperposed alignment.
 9. The device of claim 7, wherein the first andthe second superposed alignment are in position at least one on top ofthe other.
 10. The device of claim 1, wherein at least two pathways ofsaid first number of pathways are arranged electrically coupled to oneanother in a first alignment; wherein at least two pathways of saidsecond number of pathways are arranged electrically coupled to oneanother in a second alignment; wherein said first number of pathways isan odd number of pathways greater than one, and wherein said secondnumber of pathways is an odd number of pathways greater than one; andwherein a total number of pathways of said first plurality is at leastan even number greater than two.
 11. The device of claim 1, wherein atleast two pathways of said first number of pathways of said secondplurality are arranged in a first superposed alignment electricallycoupled to 095 one another; wherein at least two pathways of said secondnumber of pathways of said second plurality are arranged in a secondsuperposed alignment electrically coupled to one another; wherein atotal number of pathways of second plurality is an odd number greaterthan one; and wherein a total number of pathways of said first pluralityis at least an even number greater than two.
 12. The device of claim 10,further comprising a spacing material that at least spaces apartpathways of said circuit arrangement.
 13. The device of claim 11,wherein four pathways of the circuit arrangement are electricallyisolated from one another.
 14. The device of claim 1, wherein said firstplurality of pathways is a plurality of shielded pathways; and whereinsaid second plurality of pathways is a plurality of shielding pathways.15. An electrical arrangement comprising: at least a first and a secondplurality of pathways; wherein the first plurality includes at least onepair of pathways electrically isolated from each other and arranged inmutual complementary position; wherein at least a first number ofpathways of said second plurality is arranged electrically isolated froma second number of pathways of said second plurality, and wherein saidsecond plurality includes at least two pathways electrically isolatedfrom said first 120 plurality; wherein at least two pathways of saidfirst number of pathways of said second plurality are electricallycoupled to one another; and wherein at least two pathways of said secondnumber of pathways of said second plurality are electrically coupled toone another.
 16. The electrical arrangement of claim 15, furthercomprising a spacing material that at least spaces apart pathways ofsaid circuit arrangement.
 17. The electrical arrangement of claim 15,wherein at least four pathways of the circuit 130 arrangement areelectrically isolated from one another.
 18. The electrical arrangementof claim 15, wherein at least six pathways of the circuit arrangementare electrically isolated from one another.
 19. The electricalarrangement of claim 15, wherein said second plurality includes at leasttwo pathways arranged co-planar to one another; and wherein at leastfour pathways of the circuit arrangement are electrically isolated fromone another.
 20. The electrical arrangement of claim 15, wherein saidsecond plurality includes at least two pathways arranged co-planar toone another; and wherein at least four pathways of the circuitarrangement are electrically isolated from one another.
 21. Theelectrical arrangement of claim 15, wherein said first and said secondplurality are arranged in a non co-planar stacking; and wherein fourpathways of the circuit arrangement are electrically isolated from oneanother.
 22. The electrical arrangement of claim 15, wherein said firstplurality of pathways comprises a plurality of vias; and wherein saidsecond plurality of pathways is a plurality of shielding pathways.
 23. Adevice comprising: at least four pluralities of pathways; wherein onlyrespective pathways of each one plurality of said pluralities areelectrically coupled to one another; and wherein at least twopluralities of said at least four pluralities provide shielding for atleast two other pluralities of said at least four pluralities ofpathways.
 24. A device comprising: at least a first, a second, a thirdand a four plurality of pathways; wherein only respective pathways ofeach said plurality are electrically coupled to one another; whereinsaid first plurality shields said second plurality; and wherein saidthird plurality shields said fourth plurality.
 25. A circuit arrangementcomprising: at least a first and a second plurality of shieldingpathways; at least a first and a second plurality of shielded pathways;and wherein said shielding pathways and said shielded pathways arealternately arranged within said circuit arrangement; wherein onlyrespective pathways of each said plurality are electrically coupled toone another; and wherein each of said pluralities of said circuitarrangement are electrically isolated from one another.
 26. A system,comprising: an integrated circuit package having at least one integratedcircuit; a plurality of pathways conductively coupled together; a firstplurality of shields conductively coupled together; a second pluralityof shields conductively coupled together and electrically isolated fromat least said first plurality; and wherein each of said shields and saidpathways are alternately arranged, and wherein said shields develop atleast one low impedance pathway suitable for energy propagation awayfrom said integrated circuit; and wherein said pathways develop a lowinductance pathway suitable for energy propagation within saidintegrated circuit package, said energy propagation being conditioned190 by at least said plurality of shields.
 27. The system of claim 26,wherein said first and said second pluralities of shields arerespectively in a substantially coplanar relationship.
 28. The system ofclaim 26, wherein said first and said second pluralities of shields arerespectively in a substantially coplanar relationship.
 29. The system ofclaim 26, wherein one of said first or said second plurality of shieldscomprises a centering one of said shields, and wherein said first andsaid second pluralities of shields and said pathways are arranged in asubstantially balanced and complementary symmetrical arrangement aboutsaid centering one.
 30. The system of claim 26, wherein one of saidfirst or said second plurality of shields comprises a centering one ofsaid shields, and wherein said first and said second pluralities 205 ofshields and said pathways are substantially aligned about said centeringone.
 31. The system of claim 26, wherein each of said first pluralityand said second plurality of shields comprises an odd number of shields.32. (Currently amended) The device of claim 1 in which said device is afirst level interconnect arrangement for an integrated circuit. 33.(Currently amended) The device of claim 1 in which said device isarranged as a decoupling capacitor.
 34. (Currently amended) The deviceof claim 1 in which said device is arranged as a bypass capacitor. 35.(Currently amended) The device of claim 1 in which said device is afirst level interconnect arrangement coupled to an integrated circuit;and wherein at least said first plurality is electrically coupled tosaid integrated circuit.
 36. (Currently amended) The device of claim 1in which said device is a first level interconnect arrangement coupledto an integrated circuit; wherein said first plurality is electricallycoupled to said integrated circuit; and wherein said second plurality iselectrically isolated from said integrated circuit.
 37. A devicecomprising: a first electrically conductive shield layer that resides ina first plane; a third electrically conductive shield layer that residesin a third plane; a fifth electrically conductive shield layer thatresides in a fifth plane; said third plane is between said first planeand said fifth plane; a first electrically conductive electrode layerthat resides in a second plane, and said second plane is between saidfirst plane and said third plane; a third electrically conductiveelectrode layer that resides in a fourth plane, said fourth plane isbetween said third plane and said fifth plane; said device electricallyconnects said first electrically conductive shield layer, said thirdelectrically conductive shield layer, and said fifth electricallyconductive shield layer to one another; said first electricallyconductive shield layer, said third electrically conductive shieldlayer, and said fifth electrically conductive shield layer are stacked,said first electrically conductive electrode layer is substantiallybetween said first electrically conductive shield layer and said thirdelectrically conductive shield layer, and said third electricallyconductive electrode layer is substantially between said thirdelectrically conductive shield layer and said fifth electricallyconductive shield layer; a second electrically conductive shield layer;a fourth electrically conductive shield layer; a sixth electricallyconductive shield layer; a second electrically conductive electrodelayer; a fourth electrically conductive electrode layer; said deviceelectrically connects said second electrically conductive shield layer,said fourth electrically conductive shield layer, and said sixthelectrically conductive shield layer to one another; said secondelectrically conductive shield layer, said fourth electricallyconductive shield layer, and said sixth electrically conductive shieldlayer are stacked, said second electrically conductive electrode layeris substantially between said second electrically conductive shieldlayer said fourth electrically conductive shield layer, and said fourthelectrically conductive electrode layer is substantially between saidfourth electrically conductive shield layer and said sixth electricallyconductive shield layer.
 38. The device of claim 37 wherein: said firstelectrically conductive shield layer and said second electricallyconductive shield layer reside in a first plane; said first electricallyconductive electrode layer and said second electrically conductiveelectrode layer reside in a second plane, and said second plane isbetween said first plane and said third plane; said third electricallyconductive shield layer and said fourth electrically conductive shieldlayer reside in a third plane; said fifth electrically conductive shieldlayer and said sixth electrically conductive shield layer reside in afifth plane; and said third electrically conductive electrode layer andsaid fourth electrically conductive electrode layer reside in a fourthplane, and said fourth plane is between said third plane and said fifthplane.
 39. The device of claim 37 wherein: said first electricallyconductive shield layer, said third electrically conductive shield layerand said fifth electrically conductive shield layer are stacked uponsaid second electrically conductive shield layer, said fourthelectrically conductive shield layer, and said sixth electricallyconductive shield layer.
 40. The device of claim 39 wherein: said firstelectrically conductive electrode layer includes a first electricallyconductive electrode layer body region and a first electricallyconductive electrode layer tab region, and said first electricallyconductive electrode layer tab region protrudes from said firstelectrically conductive electrode layer body region in a first directionin said second plane; and said third electrically conductive electrodelayer defines a third electrically conductive electrode layer bodyregion and third electrically conductive electrode layer tab region, andsaid third electrically conductive electrode layer tab region protrudesfrom said third electrically conductive electrode layer body region in asecond direction opposite said first direction.
 41. The device of claim40 wherein: said second electrically conductive electrode layer includesa second electrically conductive electrode layer body region and asecond electrically conductive electrode layer tab region, and saidsecond electrically conductive electrode layer tab region protrudes fromsaid second electrically conductive electrode layer body region in thirddirection that is perpendicular to said first direction and said seconddirection; and said fourth electrically conductive electrode layerdefines a fourth electrically conductive electrode layer body region andfourth electrically conductive electrode layer tab region, and saidfourth electrically conductive electrode layer tab region protrudes fromsaid fourth electrically conductive electrode layer body region in afourth direction opposite said third direction.
 42. The device of claim37 further comprising additional electrically conductive electrodelayers and additional electrically conductive shield layers.
 43. Thedevice of claim 37 further comprising an electrically conductiveinterconnections between two layers of said device.
 44. The device ofclaim 37 further comprising a sixth electrically conductive shield layeradjacent said first electrically conductive shield layer, and a seventhelectrically conductive shield layer adjacent said fifth electricallyconductive shield layer.
 45. The device of claim 37 further comprising:a set of electrically conductive interconnections; a set of padsprotruding from a surface of said device, and wherein each one of saidset of electrically conductive interconnections connects to a differentone of said set of pads.
 46. The device of claim 45 wherein at leastsome of said set of pads are designed for connection to an integratedcircuit.